As chip-design geometries shrink, the device operating voltages also reduce, resulting in lower breakdown voltages of the on-chip components. However it still remains necessary for the chip to communicate with external circuitry, which may be operating at higher voltages that may often exceed the break down voltages of the on-chip components. In such situations it is important to ensure that the on-chip components are not exposed to high voltage stresses.
FIGS. 1A and 1B show a scheme for protection of digital devices in CMOS technology from high voltage stresses in accordance with U.S. Pat. No. 5,892,371, which is incorporated by reference. This scheme uses special protection transistors biased with reference voltages, Vrefn and Vrefp inside standard digital gates.
This scheme for protecting digital logic suffers from the drawback that it can only be used with digital circuits and is not suitable for analog circuits. Also the use of special protection transistors with each gate results in a heavy penalty in terms of chip area. In the case of universal gates such as a NAND or NOR gates, the addition of the protection transistors also reduces the operating speed. Therefore, when these gates are used in large numbers in a macro cell, not only will the area overhead increase, but the speed of operation of such a cell would also decrease. Such a scheme is also not suitable for analog circuits.
FIG. 2 shows the scheme for generating the reference voltages Vrefn and Vrefp of FIGS. 1A and 1B according to U.S. Pat. No. 5,923,211, which is incorporated by reference. This scheme uses a Bandgap Voltage Reference and two Operational Amplifiers.
Since Vrefn and Vrefp have a finite settling time which depends on the bandwidth of the Bandgap Voltage Reference and the two Operational Amplifiers, the protection mechanism would typically operate a short time after the application of the power supply. During this period the circuit is often unprotected and subjected to the voltage stresses imposed by the power supply and/or the interface signals. The Bandgap Voltage Reference and the two Operational Amplifiers themselves are also often subject to such voltage stresses during this period particularly when these are operated on a supply voltage greater than the breakdown voltage of the constituent transistors.